not-yet-known not-yet-known not-yet-known unknown A 0.9-V low-power VCO by using TSMC 0.18-μm CMOS process has been proposed. A cross-coupled gain enhancement multiple-gate circuit is proposed for lowering phase noise. The gates of the tail transistors are driven by the differential fundamental oscillation signals from the cross-coupled pair. The second order harmonic signals of the oscillation signals at the drains of the tail transistors can be enlarged. The proposed circuit uses the enlarged second order harmonic signals for increasing the differential fundamental signal power without extra power consumption. The proposed circuit can also provide higher output impedance and voltage gain than conventional common-source cross-coupled pair. The measured results show the phase noise at 1 MHz offset frequency from the carrier signal is -119.2 dBc/Hz with 1/f3 corner frequency of 21 kHz while the control voltage is 0.5 V. The frequency tuning range is from 2.29 to 2.37 GHz under power consumption 1 mW. The figure of merit at 1 MHz offset frequency from the carrier signal is -187 dBc/Hz.

A 0.6-V low-power VCO by using TSMC 0.18-μm CMOS process has been proposed. For lowering phase noise, injection-locked enhancement and bulk-driven technologies are proposed. The injection-locked enhancement technology reuses second order harmonic signals of the oscillation signals through the injection-locked capacitors with the enhancement circuit. The buck-driven technology provides extra transconductance for the cross-coupled pair. The proposed technologies can enlarge the fundamental signal power of the oscillation signals for lowering the phase noise. The measured results show the phase noise at 1 MHz offset frequency from the carrier signal is -118.16 dBc/Hz with 1/f3 corner frequency of 23 kHz while the control voltage is 0.6 V. The frequency tuning range is from 2.33 to 2.37 GHz under power consumption 1.3 mW. The figure of merit at 1 MHz offset frequency from the carrier signal is -184.43 dBc/Hz.