DAC mismatch is the bottleneck for data converters to achieve high resolution. The error-feedback mismatch error shaping (EF-MES) is an effective method to address the DAC mismatch. However, the existing EF-MES can only achieve the 1st-order shaping for continuous-time (CT) DACs. This letter proposes the methodology and implementation details of a 2nd-order EF MES for CT DACs. This method can also be generalized to arbitrarily high-order EF MES.

The kT/C cancellation technique can effectively reduce the DAC size for SAR ADCs and thus relax the burden for input drivers and ref-erence buffers. However, the prior kT/C cancellation technique suffers from a hard trade-off between the noise, amplifier bandwidth and linearity. In this work, an improved kT/C noise cancellation technique is proposed to break the trade-off. It uses presampling to hold the input signal unchanged during the noise cancelling phase, leading to sig-nificantly relaxed requirements on the bandwidth and linearity of the amplifier. The proposed technique is verified in a 14-bit 200MS/s SAR ADC with the DAC size of 128 fF. Simulation results show that this work achieves 75.6 dB SNDR and consumes 1.56 mW power.

The fully passive noise shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) are simple, OTA-free and scaling friendly. Previous passive NS-SAR ADCs rely on the multi-path-input comparator or capacitors stacking to realize the passive gain for compensating the signal attenuation during passive integration. However, the former causes high comparator power consumption, and the latter suffers from additional signal attenuation due to the parasitics and is hard to extend to high-order systems. This work proposes a new fully passive NS-SAR technique, it can realize 2× gain with a simple structure, leading to the reduced comparator power and less parasitics. This technique is also easy to extend to high-order NS-SAR ADCs.