Fig. 4. Output impedance characteristic of PMOS, GC-FVF and FVF topologies.
For FVFs, at low frequency, the low impedance affects its loop gain, and at high frequency, the impedance may increase, further affecting its loop stability. The proposed GC-FVF has a moderate output impedance at low frequency that is between the PMOS FVF and the conventional PMOS structures, which avoids its DC gain from being small. At high frequency, C1 is considered to be a relatively opening path, so the PMOS FVF works, reducing the variation of its impedance with frequency. Intuitively, the GC-FVF structure utilizes the impedance characteristic of the gate-couple capacitor, which can block the DC voltage while allowing the PMOS FVF structure to work at small-signal state without affecting the output voltage swing of the LDO.
Fig. 5 shows the output impedance with frequency of the LDO with GC-FVF structure. gm1 is a constant, whilegmp is determined by the load current. As the load current Iload varies from a light load of 10μA to a heavy load of 100mA, the transconductance of the pass transistor increases, resulting in the decrease of the output impedance. Importantly, there will be a large peak at 15MHz under light loads, while such problems will not occur under heavy loads.