Fig. 5. Output impedance characteristic of the proposed GC-FVF
LDO.
3. Circuit implementation
Fig. 6 shows the overall structure of the proposed GC-FVF LDO. The error
amplifier (EA) consists of a single-stage folded cascode structure, with
the PMOS M1 and M2 being the input stage. According to previous
discussions, the output swing of FVF structures such as STC-LDO in
[5] is severely limited, and a NMOS is consequently required as the
input pair. M9 is a PMOS buffer with a small output impedance, which
pushes the poles at N1 to a high frequency. The common source gain stage
is achieved through the power PMOS MP and constitutes the second gain
stage in the LDO to drive the on-chip output capacitor CL. On-chip
resistors R1 and R2 form a negative feedback by sampling the output
voltage and feeding it back to the noninverting input terminal of the
EA. Therefore, the obtained LDO structure can be considered as a
two-stage amplifier.
Fig. 6 Structure of the proposed LDO with Gate-Couple FVF scheme
3.1. Frequency compensation method
The proposed LDO is stabilized by a cascode miller frequency
compensation, which is a kind of pole-splitting compensation method. The
compensation capacitor Cc provides a low-frequency pole for the
two-stage amplifier to achieve stability over the entire range of load
current. In this two-stage amplifier design, the use of a cascode miller
frequency compensation scheme enables the amplifier to achieve a wider
unity-gain frequency and higher stability by removing the right half
plane zero point, as well as enhances the PSRR [2].
In addition, and more importantly, this compensation design is used to
split the pole at the LDO output, allowing the LDO to achieve stability
throughout the entire load current range by using only small
compensation capacitors. Fig. 6 shows the cascode Miller frequency
compensation in the proposed LDO, implemented by Cc and transistor M3.
3.2. Proposed GC-FVF output stage
The proposed GC-FVF structure consists of M5, C1 and MP in Figure 6. M6
and M24 provide the gate bias voltage and drain bias current for M5
respectively, and the GC capacitor C1 is coupled from the drain of M5 to
the gate of the transistor MP.
The output voltage range of this LDO is given by
where VGS and VDS, satrepresent the gate-to-source and overdrive voltages, respectively.
The FVF output stage can be considered as a fast loop, which has been
analyzed in the previous section that can provide output impedance
attenuation without affecting the output voltage swing or load current
range. It can be inferred that the attenuated output impedance and the
small on-chip load capacitance keep the output pole constantly away from
the unit gain bandwidth. It is worth mentioning that this fast loop has
a role in transient response.
3.3. Stability Analysis
It is important to analyze the stability of the proposed LDO using the
loop gain transfer function. Figure 7 is the small signal block diagram
of the circuit in Fig. 6, used to analyze the open-loop transfer
function. The gm1 , gm3 ,gm5 , and gmp in Fig. 6
represent the transconductance of the input differential stage M1/M2,
current buffer stage M3, gate-couple feedback input stage M5, and power
transistor MP, respectively. In addition, β =R2/(R1+R2) is the
feedback coefficient. The output of the source follower N1 is a low
impedance node, so the parasitic capacitance here is ignored in the
analysis. The loop gain transfer function is given by
Based on the above settings, the zero can be ignored and the poles of
the proposed GC-FVF LDO are given by
Fig. 7 Small-signal block diagram of the proposed LDO with
current-buffer compensation scheme.
The following points are referred to:
- The GC-FVF structure makes little variation of the output impedance
within the unity-gain bandwidth.
- The minimum current and gm of MP is limited by the DC operating points
of M5 and M6.
- No large off-chip load capacitance.
Therefore, under both light and heavy loads, the value ofRout_eqCL is a relatively small,
so the circuit can be regarded as a stable two-pole amplifier system
composed of ωP1 and ωP2 .
Figure 8 shows the bode plot of the proposed GC-FVF LDO. It can be seen
that under heavy load, due to the decrease in gain, the main poleωP1 is extrapolated, but it is still relatively
far away from the non-dominant pole. Figure 8 shows that the phase
margin remains almost unchanged under light and heavy loads.
Fig.8 Simulated loop-gain transfer function of the proposed
GC-FVF LDO.
4. Simulation result
To test and verify the proposed GC-FVF LDO, this chip is shown in Fig. 6
which is manufactured in a 0.18μm standard 5V CMOS process. Fig. 9 shows
the layout of the proposed LDO, with an effective area of 260μm×180μm.
The regulator is designed to provide a load current of 0-100 mA with an
output voltage of 1.8 V from a 2 to 5V supply. The dropout voltage is
about 200 mV at the maximum Iload .
Fig. 9 Layout of the proposed GC-FVF LDO
The line regulation and load regulation
Benefiting from a stable two-pole system, the loop gain of the proposed
LDO can exceed up to 100dB. And the load and line regulation are given
by
Fig. 10 shows the load transient response of the GC-FVF LDO at a Vin of
3.3V. Fig. 11 shows the line regulation from 0mA to 100mA at Vin=2V,
2.5V and 3.3V. The measured line and load regulations are 13.8 μV/V and
4.8 μV/mA, respectively.
Fig. 10. Simulated load transient response
Fig. 11. Simulated load regulation
Transient response
Compared with the example in [12] without off-chip capacitors, the
proposed LDO has an improved transient response. Fig. 11 depicts the
measured transient response with an on-chip load block whose current
changes from 0mA to 10mA, 50mA and 100mA within 1μs. Under a large load
step change from 0mA to100mA, the transient overshoot and undershoot are
367mV and 202 mV. The proposed GC-FVF loop improves the transient
response of the LDO without off-chip capacitors, and the good transient
stability of the output voltage further proves the large phase margin
achieved in the proposed LDO.
To compare this work with other LDOs in the literature, widely used
figure-of-merit (FOM) are adopted from [11]. The FOM is defined as
where TR is the transient response time,IQ is total quiescent current andIMAX is the maximum load current. This indicates
that LDOs with better power consumption and transient performance have
lower FOM.
Table 1. Performance comparison with related works.
(*Experimental Results)