Table. 1 shows that the proposed LDO has a low quiescent current of
32μA, resulting in better FOM compared to the LDO in [10] without
off-chip capacitors. With a low output impedance within the unity-gain
bandwidth, the proposed LDO still has a wide input voltage swing, while
the input voltage of the conventional FVF LDO in [5] must be about
one VTH larger than VOUT. In addition,
benefiting from high loop gain, this LDO has better load regulation of
4.8μV/mA and line regulation of 13.8μV/V compared to those in [7-8]
while maintain a small area about 0.047 mm2 and low
power dissipation of 32μA.
5. Conclusion
This work proposes an LDO based on GC-FVF structure. The proposed GC-FVF
structure solves the swing problem of PMOS FVFs as the output stage,
while retaining the low output impedance characteristic. This, combined
with cascode Miller frequency compensation, can generate two stable
poles inside the LDO, while the output pole is pushed far away from the
unity-gain frequency.
The simulation results show that the GC-FVF LDO has improved transient
response compared to other LDOs without off-chip capacitor. And this
chip has a wide input and output range, high load and linear regulation,
low quiescent dissipation, and high load current.