A Capacitor-Free CMOS Low-Dropout Regulator with Gate-Couple Flipped Voltage Follower for SOC

Yani Li, Fuxiang Tong*, Zuoyi Zhang, Zhuo Lv, Linkun Zhang, Zhangming Zhu

Yani Li, Fuxiang Tong, Zuoyi Zhang, etc. are all with Shaanxi Key Lab of Integrated Circuits and Systems, School of Microelectronics, Xidian University, 2 South Taibai Road, Xi’an, 710071, P. R. China. (E-mail: 21111212988@stu.xidian.edu.cn).

Keywords: flipped voltage follower (FVF), low dropout (LDO) regulator, output impedance, power electronics

This paper proposes a fully integrated low dropout (LDO) regulator with gate-couple flipped voltage follower(GC-FVF). The proposed GC-FVF addresses the limited output swing issue of conventional PMOS FVF in LDOs while maintaining a low output impedance. Besides, this LDO introduces a cascode compensation loop, which, along with the low output impedance of GC-FVF, pushes the output pole far away from the unity-gain bandwidth under both light and heavy load conditions. Consequently, the LDO becomes a stable two-pole system, supporting a high loop gain of up to 100dB and significantly enhancing the load and line regulation. Key specifications include a preset output voltage of 1.8V, a minimum unregulated input voltage of 2V, a maximum output current of 100mA, a ground current of 32μA, and an active chip area of 260μm×180μm. Notably, this LDO achieves high load regulation of 4.8μV/mA and high line regulation of 13.8μV/V without the need for off-chip capacitors.

1. Introduction

As an important research field in analog chips, power management is widely used in various electronic products. The low dropout voltage (LDO) regulator is one of the most considerable power management modules, which can provide an adjustable low noise and precise power supply voltage for noise sensitive analog blocks. The characteristics of LDOs make them widely used in highly integrated electronic devices such as mobile phones, pagers, video recorders, laptops. In addition, the improvement of integration level in portable devices not only requires LDOs to provide high load current, but also requires LDOs to minimize no-load quiescent current to extend battery life [1-2]. In many existing topologies, the LDO based on the fully integrated flipped voltage follower (FVF) is an attractive choice due to its low output impedance, fast transient response, and relatively small area [3-6].

Fig.1(a) shows the conventional CD amplifier structure, which needs a current bias from the positive supply. Fig. 1 (b) shows the conventional PMOS FVF circuit [4]. The gate of M2 is connected to the feedback terminal V_FB, forming a local feedback loop, which significantly reduces the output impedance [6]. According to the comparison, it can be found that FVFs can be considered as a variant of a common drain (CD) circuit with local feedback.

One major drawback of the conventional PMOS FVF in Fig.1(a) is the limitation on the minimum and maximum load currents and output voltage [3]. If the load voltage is less than the minimum value, the gate voltage of M2 increases to reduce the overdrive voltage, which pushes M1 out of saturation. That is undesirable for the normal function of LDO. And under high load current, the output dominant pole may approach the internal non-dominant pole, resulting in poor phase margin. Besides, due to the low loop gain of FVF, this type of LDO has a substandard load regulation. The poor load regulation is also due to the lack of tight coupling between V_OUT and V_REF.

Fig. 1. (a). CD amplifier, (b) PMOS FVF structure, (c) Proposed GC-FVF structure

The output voltage range of the PMOS FVF circuit is given by the following equations:

where V_SG and V_{SD, sat}represent the source-to-gate and overdrive voltages, respectively.

Fig. 2. The single transistor controlled FVF LDO in [5]

The single transistor controlled LDO in [5] based on PMOS FVF is shown in Fig. 2, which consists of an error amplifier (EA), a V_SET generation stage, and an FVF output stage. The voltage V_MIR is adjusted by EA to set V_MIR equal to V_REF. V_SETgeneration stage establishes a correlation between V_MIRand V_OUT. The transistor M3 connected to V_SET through a diode is kept one V_SGbelow V_MIR. It can be observed that V_MIRand V_OUT are equal.

Fig. 1 (c) illustrates the proposed GC-FVF structure, separating the drain of M1 from the gate of M2 by using a coupling capacitor C1, which maintain the advantage of small impedance without shrinking the output swing.

The proposed GC-FVF structure solves the voltage swing problem of a PMOS FVF as the output stage, while retaining the low output impedance characteristic of PMOS FVFs.

The organization of this article is as follows: Section Ⅱ describes the implementation details of the proposed GC-FVF structure. Section Ⅲ analyzes the overall loop of LDO with the proposed GC-FVF as the output stage. Section Ⅳ presents simulation results and compares them with other literature. Section Ⅴ discusses the conclusions.

2. Proposed Gate-Couple Flipped Voltage Follower

As shown in Fig. 3(a), the drain of M1 is separated from the source of MP by using a capacitor C1. MP is the power transistor for this LDO. The gate of M1 has been changed to connect a bias voltage instead of a reference voltage in FVFs. The parasitic capacitors C_{GS, pass}, and C_{GD, pass} associated with MP are large and usually comparable to the output capacitor. At low frequency, as illustrated in Fig. 3(b), C1 is considered to be open. However, at high frequency, C1 is considered to be a relatively opening path, at which point the FVF structure works, as illustrated in Fig. 3(c).

Fig. 3. (a). GC-FVF structure, (b) Situation at low frequency, (c) Situation at high frequency

Two different operating modes between high and low frequency keep the output impedance change within a moderate range. And the isolation of the capacitor can eliminate the impact of the DC voltage of MP’s gate on the DC operating point of M1.

The proposed GC-FVF structure maintains low output impedance in unity-gain bandwidth while allowing the swing of the output voltage V_OUT to be independent of the load current. According to the calculation of vx and ix in Fig. 3(a), the small signal output impedance under typical application conditions of the proposed GC-FVF structure can be calculated as follows:

where C_tot =C₁+C_GD+C_GS . Parameters g_m1 and g_mrepresent the transconductance of M1 and MP.

In the case of an FVF application where g_m1 andg_mp are approximately equal. AndC₁ >>C_GD, C_GS, poles ω_P1 andω_P2 are given by

The molecule of the impedance transfer function represents the existence of a zero in the left-half-plane (LHP), which is given by

The impedance comparison diagram of the conventional PMOS, PMOS FVF, and Gate-couple FVF is illustrated in Fig. 4. As shown, the appearance of the zero point stabilizes the impedance in the mid frequency range, while at high frequency, the impedance is similar to that of FVFs.