A three-step discrete-time incremental analog-to-digital converter (IADC) combines zoom, IΔΣM and dual-mode SAR-assisted extended counting (EC). The IADC reuses the SAR ADC to reduce hardware cost by reconfiguring its DAC array to either a 2-bit quantizer of the core IΔΣM or a 5-bit EC ADC. Clocked at 4MHz with an OSR=99, the proposed IADC achieves SNDR and DR of 93dB and 98.5dB, respectively, in a BW of 20.2kHz.