E-mail address: jijuntong@zstu.edu.cn.
Abstract: Variable supply voltage-clustered voltage scaling (VS-CVS) is an effective way to decrease power consumption without compromising performance. One of the major challenges in VS-CVS design is that level converting flip-flops(LCFFs) not only need to have low power consumption but also high performance. In this paper, we propose two new structures of LCFF: the data branch sharing LCFF based on conditional charging (DBS-LCFFCC) and the data branch sharing LCFF based on precharging (DBS-LCFFP).The new structures adopt a data branch sharing scheme to improve the speed of the circuit as well as to reduce the number of transistors. Based on simulation results using HSPICE with PTM 32nm CMOS technology, the proposed LCFFs show an improvement of 19.2% to 67.2% and 41.6% to 76.3% in power-delay-product (PDP) at 50% data switching activity, respectively, compared to other advanced LCFFs.
Keywords: level-converting flip-flop; pulse triggered; low power; PDP
Introduction
With the development of very large scale integration (VLSI) systems, balancing power consumption and delay has become one of the biggest design challenges. The clock system is one of the most power-consuming parts of a VLSI system, accounting for 25% to 40% of total system power consumption [1]. Flip-flops are very critical parts of the clock system, so reducing the power consumption and delay of flip-flops has a profound impact on the total power consumption and delay of the entire VLSI system[2].
As power consumption is proportional to the square of the voltage, voltage scaling is the most effective way to reduce power consumption [3]. However, reducing the supply voltage causes an increase in circuit delay. Therefore, the variable supply voltage-clustered voltage scaling (VS-CVS) technique has been adopted for low-power systems. In this technique, the critical path is assigned to high supply voltage (VDDH) to maintain circuit performance, while the non-critical path is supplied with low supply voltage (VDDL) to reduce circuit power consumption. In the VS-CVS system, the high-voltage block can drive the low-voltage block directly. However, when the low-voltage block drives the high-voltage block, the PMOS transistor in the pull network on the high-voltage circuit cannot be fully closed, increasing the static power consumption. Therefore, when the circuits need to be connected with different supply voltages, it is necessary to employ a level converting flip-flop (LCFF) as an interface to complete the level conversion function [4-8].
Although several LCFFs have been proposed in the existing literature, there are still some drawbacks [9-13]. For instance, the required number of transistors is excessive, the power consumption is too large, and the delay is relatively high. To solve the above issues, in this paper we propose two data branch sharing dual-edge explicit-pulsed level converting flip-flops (DBS-LCFF). One of the DBS-LCFFs is based on conditional charging (DBS-LCFFCC) and the other DBS-LCFF is based on precharging (DBS-LCFFP). Based on data branch sharing technique, the proposed LCFFs can reduce the number of transistors and decrease the delay. Among them, DBS-LCFFCC can further reduce the power consumption, while DBS-LCFFP can further reduce the delay.
The rest of this paper is structured as follows. Section 2 reviews several existing level converting flip-flops. In Section 3, two novel data branch sharing level converting flip-flops are proposed. In Section 4, the proposed level converting flip-flops are simulated and compared with other flip-flops. Section 5 concludes the whole paper.
Previous level converting flip-flops Design
Compared to the master-slave structure level converting flip-flop, the pulse-triggered level converting flip-flop has a simpler structure and smaller delay. The pulse-triggered level converting flip-flop is divided into two types: implicit and explicit structures. The explicit structure has a smaller delay and can share a pulse signal generator with multiple flip-flops. This section mainly introduces several explicit pulse-triggered level converting flip-flops.
Fig. 1 shows the dual-edge triggered level converting flip-flop (DE-LCFF) [9], which is a dynamic flip-flop with node X precharged to VDDH by the full-swing pulse generated by the dual pulse generator. The input signal D, after passing through the sampling circuit, still needs to pass through two inverters to reach the output signal Q, which will cause a large delay. Another drawback is that when the input signal D keeps high, the dynamic power consumption is high due to the redundant switching activity of the internal node X. In addition, the DE-LCFF uses 33 transistors, which further increases the power consumption and area overhead.
The double-edge triggered levelĀ converter flip-flop with feedback (LCFFF) [10] is shown in Fig. 2. The LCFFF employs conditional discharge to reduce power consumption and the precharge technique to increase circuit speed. However, the pulse generator produces pulses differently at the rising and falling edges of the clock, resulting in asymmetry between the two pulses. This asymmetry may affect the stability of the circuit. In addition, the pulse generator requires large inverters to generate narrow pulses, resulting in significant power consumption.