Fig. 8. The proposed LCFFs simulation waveform graph.
The proposed LCFFs are compared to the LCFFs presented in Section 2 in
terms of performance.For the PTM 32nm process technology, all LCFFs are
optimized to achieve the minimum power-delay product (PDP). The
experimental conditions specified previously apply to this experiment.
Table 1 shows the delay data for each LCFF obtained from the simulation.
Among them, D↓C↓ (or D↑C↓) denotes the minimum D-Q delay at the falling
edge of the clock when the input signal D switches from ”1” to ”0” (or
”0” to ”1”). D↑C↑ (or D↓C↑) denotes the minimum D-Q delay at the rising
edge of the clock when the input signal D switches from ”0” to ”1” (or
”1” to ”0”). The average delay is the average minimum D-Q delay for the
four cases.
Table 1. Delay comparison of various LCFFs