(a) (b)
Fig. 6. (a) Clock pulse generator; (b) Novel double edge
triggered level converter flip-flop (nDE-LCFF).
Proposed level converting flip-flops
The existing level converting flip-flops have various problems, such as
an excessive number of transistors, high power consumption, high delay,
etc. Therefore, two level converting flip-flops are proposed in this
paper to solve the above problems. This section mainly introduces the
structure and working principle of the proposed level converting
flip-flops.
The proposed duoble edge clock pulse generator is shown in Fig. 7(a)
shows. It utilizes three cascaded inverters to generate delay signals
CLK1, CLK2, and CLK3 from the clock signal CLK. Transistors P1 and P2
form a two-input transmission gate, where the clock signal CLK and its
inverse delay signal CLK1 drive the gates of P1 and P2, respectively,
and CLK2 and CLK3 serve as the two input signals of the two-input
transmission gate. When CLK changes from ”1” to ”0”, transistor P2 turns
on, CLK2 remains ”1”, and node A outputs a high level to make transistor
N1 turn on. Node X discharge to ”0” by transistor N1, and then the pulse
signal is generated by the inverter. After two inverter delays, CLK2
also becomes ”0”, transistor N1 turns off, and the pulse signal returns
to the low level. When CLK1 changes from ”1” to ”0”, transistor P3 turns
on. The situation here is exactly similar to the above analysis, so we
will not repeat it. The above discussion shows that the proposed pulse
generator is a double-edge pulse generator with a pulse width of two
inverter delays.