Fig. 3 Proposed 16 x 16 signed multiplier with radix-8 architecture
The two 3-bit groups in stage-1 use two 8:1 MUXs of 10-bits,\(N+2\) bits, wide to choose from one of the eight possible values, trivial and non-trivial. The lone bit,\(B_{p}\left[6\right]\), with logic ‘1’ generates X(\(A_{p}\)) as PP and with logic ‘0’ generates all 0’s resulting in the third PP which is being reduced in stage 2. The 15-bit, \(2N-1\), product magnitude generated, \(z\left[14:0\right]\), is finally 2’s complemented, and the two values fed into 15-bit,\(2N-1\), wide 2:1 MUX to choose the magnitude based on the sign of the actual operands. The final MUX deals with the highest magnitude case where it skips the value from the previous stages and sets the final sum, \(Z[15:0]\), to be the left shifted (by\(N-1\) bits) value of the complimented multiplicand, \(A_{c}\). With this discussed technique, a 16 x 16 multiplier is designed as shown in Fig. 3. Compared Fig. 1 and Fig. 3, 16 x 16 multiplier requires 3 stages, \(\operatorname{}{(N)}-1\) stages, of PP reduction. Similarly, 32 x 32 and 64 x 64 multipliers require 4 and 5 stages of PP reduction respectively.
Table 2: Complexity comparison between conventional Booth architecture and the proposed radix-8 architecture.