The designs in [1] and [2] are implemented in 32nm CMOS
technology along with these proposed designs. All three designs include
input and output registers, and the simulation results are summarized in
Table 4. Power values included and PDP values computed are
rounded to two decimal places. Performance results for the 16-bit
multiplier presented in [4 ] are normalized to the current
technology for fair comparison. The delay and area of the wider
multipliers using the architecture in [2 ] are estimated to
increase at a rate of 2x and 4x respectively with the increase in size
of the operands by twice whereas the delay of the proposed designs
increase at a rate between 1.5x to 2x. Comparing the estimated delay
values of the 32- and 64-bit post-layout designs using the modified
Booth algorithm in [2] with this proposed radix-8 architecture show
a decrease in delays by 0.47% and 18.04% respectively. The decrease
rate grows exponentially for more wider designs.
Table 4: Performance comparison of signed multiplier designs.