Hardware complexity is shown in Table 2, for the conventional and the modified Booth architectures . The conventional Booth architecture generates \(\frac{N}{2}\) PPs requiring \(N/2-1\)additions for reduction. The proposed radix-8 structure generates\(\sim N/3\) PPs requiring 3 additions for the NT computation block in the overhead stage and \(N/3-1\) for the PP reduction.

Optimized PP grouping & BEC (Binary Excess-1 Code)-like structure: The new grouping strategy emphasizes the use of the light weight BEC-like structures , to reduce the power consumption and design area with high speed. 6-bit BEC-like structure is shown in Fig. 4 and used in 16 x 16 multiplier design in Fig. 3, on the MSB side of stage 2 and stage 3.