Fig. 4 6-bit BEC-like structure
The Boolean equations for the 6-bit BEC-like structure in Fig. 4
are expressed in (1) below, which computes the BEC on Cin=1 and
yields identity on Cin=0.
\begin{equation}
e_{0}\mathbf{=}C_{\text{in}}\mathbf{\bigoplus}a_{0}\nonumber \\
\end{equation}\begin{equation}
e_{1}\mathbf{=}\left(C_{\text{in}}\cdot a_{0}\right)\mathbf{\bigoplus}a_{1}\nonumber \\
\end{equation}\(e_{2}\mathbf{=}\left(C_{\text{in}}\cdot a_{0}\cdot a_{1}\right)\mathbf{\bigoplus}a_{2}\)\(\left(1\right)\)
\(\cdots\)\(e_{5}\mathbf{=}\left(C_{\text{in}}\cdot a_{0}\bullet\cdots\bullet a_{4}\right)\mathbf{\bigoplus}a_{5}\)
Final design performance: The proposed designs (8 x 8, 16 x 16,
32 x 32, 64 x 64) are designed in 32nm CMOS technology at 1.0 V supply
voltage, including synthesis and placement & routing (PnR) using
Synopsys DC and ICC tools. All the designs include input and output
registers.
The synthesis results for the sub-components, shown in Table 3, used in
designing the proposed 8 x 8 and 16 x 16 multipliers include only
the combinational area and power. BEC-like structure usage is
employed because of its faster and smaller design. Timing uncritical
additions on the MSB side involve simple Ripple Carry Adders(RCA).
Table 3: Synthesis results for the sub-components used in the 8
x 8 and 16 x 16 signed multiplier designs proposed