References
1. Xue, H., Patel, R., Boppana, N.V.V.K., Ren, S.: ‘Low-power-delay-product radix-4 8*8 Booth multiplier in CMOS’,Electronics Letters, 2018, 54 , (6), pp. 344-346, doi: 10.1049/el.2017.3996
2. Boppana, N.V.V.K., Kommareddy, J., Ren, S.: ‘Low-Cost and High-Performance 8 × 8 Booth Multiplier’, Circuits, Systems, and Signal Process., 2019, 38 , (9), pp. 4357-4368, doi: 10.1007/s00034-019-01044-x
3. Boppana, N.V.V.K., Ren, S.: ‘A low-power and area-efficient 64-bit digital comparator’, Journal of Circuits, Systems and Computers , 2016, 25 , (12), pp. 1650148–1650163, doi: 10.1142/s0218126616501486
4. Gorgin, S., Jaberipur, G.: ‘Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication’, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 25 , (1), pp. 75-86, doi: 10.1109/TVLSI.2016.2579667
5. Chuang, P.I.-J., Sachdev, M., Gaudet, V.C., ‘A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS’, IEEE Transactions on Circuits and Systems I: Regular Papers, 2013, 61 , (1), pp. 160-171, doi: 10.1109/TCSI.2013.2268591