The design principle is illustrated in Fig. 1, block diagram, and Fig.
2, computation procedure. First computes the magnitudes,Ap (X) and Bp of the operandsA and B using two B2C and two MUX blocks in
precomputation stage. Trivial (T) and NT values (based on
the split shown in Table 1) are computed in the pre-computation stage.
Trivial value generation does not require any hardware while non-trivial
value generation is performed using the NT block resulting in the
pre-stage outputs \(P(NT1)\), \(Q(NT2)\), and \(R(NT3)\), as shown in
Table 1 and Fig. 1. The \(N\) bit sign number magnitude does not exceed\(N-1\) bits except for the maximum magnitude case, where only the MSB
bit is a logic ‘1’. This special case is dealt separately in the final
stage just by selecting the \(A_{c}\) left shifted by \(N-1\) bits.
Otherwise, the 7-bits, in the case of 8-bit multiplier, are grouped into
two groups of 3-bits, \(B_{p}\left[5:3\right]\) and\(B_{p}\left[2:0\right]\), and one lone bit,\(B_{p}\left[6\right]\).