As machine learning (ML) algorithms, particularly neural networks (NN), expand in popularity and capacity, the quest for more efficient computation methods gains momentum. Memristor crossbar technology emerges as a promising alternative to traditional computing units, aiming to address traditional computing challenges. However, conventional matrixvector multiplication (MVM) methods on these platforms are often plagued by device imperfections and drift. In this work, we introduce an innovative lightweight calculation approach leveraging bit-transformation for MVM, significantly enhancing operation precision and, consequently, the performance of ML algorithms on memristor crossbar platforms. We provide details of the core algorithm and its extensions, furnish digital validation, and simulate its efficacy using an autoencoder (AE) neural network with an extended VTEAM model. Our tests demonstrate an average reconstruction precision improvement of approximately 53.5%. This work's applicability extends beyond NNs, offering a foundational method for conducting more precise analog MVM operations.

Spiking neural networks (SNNs) possess biological plausibility and energy efficiency as they communicate using asynchronous and mostly sparse spikes. These features make them an ideal choice for efficient neuromorphic computing. The non-differentiable, discrete binary spike events transmitted in SNNs pose a challenge for applying gradient-based optimization algorithms directly to these networks. Therefore, efficient techniques are necessary to enhance energy efficiency without sacrificing accuracy. In this work, we propose Spike Timing Dependent Gradient (STDG), a fast and lightweight learning scheme that uses temporal locality among spikes to avoid non-differentiable derivatives. Our experiments show that STDG reaches the state-of-the-art accuracy of 99.5% and 98.2% on the Caltech101 face/motorbike and the MNIST datasets, respectively.

In this study, we present an analog-to-digital converter (ADC) optimized for implantable neural interfaces. The proposed ADC integrates a series of memristors in both the input and feedback Digital-to-Analog Converter (DAC), significantly boosting the input impedance and making it suitable for neural interfaces. A defining feature of the ADC is the ability of the memristor resistance to adapt to various conditions such as large DC offset, motion, and stimulation artifacts. The model was simulated using 65nm MOSFET technology along with a physical memristor model, yielding an impressive signal-to-noise-and-distortion ratio (SNDR) of 62.7dB and a substantial Nyquist sampling rate of 50kHz. Power consumption is remarkably low, with less than nW for integrators, 5µW for the comparator, and 0.45 µW for the feedback DAC-a key requirement for neural interfaces implanted in the brain. The ADC demonstrates strong resilience against component mismatch, maintaining circuit stability even in variable conditions. Through its ability to adjust input resistance, the ADC can enhance its SNDR. This adaptive and robust ADC design shows promising potential for implantable neural interface applications.

A universal objective function to minimize mem-ristive crossbar deep neural network weight mapping errors through Hessian backpropagation (HessProp) is presented. Hes-sProp minimizes the L2 norm of the neural network gradient to achieve a flat minima in a neural network's weight space. We hypothesize that this leads to robustness against small perturbations of weights. The stochastic weight mapping phenomenon on memristor crossbars is simulated, and the proposed method was evaluated on image classification tasks using the MNIST dataset. The result demonstrates on average 40.81% and 41.45% groundbreaking accuracy increase for distilled and large memristive convolutional neural networks in worst-case scenarios.

Single-cell RNA sequencing is an emerging technique in the field of biology that departs radically from the previous assumption of gene-expression homogeneity within a tissue. The large quantity of data generated by this technology enables discoveries of cellular biology and disease mechanics that were previously not possible, and calls for accurate, scalable, and efficient processing pipelines. In this work, we propose SSCAE (spiking single-cell autoencoder), a novel SNN-based autoencoder for sc-RNA-seq dimensionality reduction. We apply this architecture to a variety of datasets, and the results show that it can match and surpass the performance of current state-of-the-art techniques. Moreover, the potential of this technique lies in its ability to be scaled up and to take advantage of neuromorphic hardware, circumventing the memory bottleneck that currently limits the size of sequencing datasets that can be processed.

In this work, ensemble methods are presented and tested as universal ways to improve the performance of Mem-ristive Deep Neural Networks (MDNNs) with non-idealities. The Generalized Ensemble Method and Weighted Voting ensemble methods improve the accuracy of classification on the MNIST dataset by 6.5% and 6.6% respectively, thus showing that they are more effective than basic Ensemble Averaging which has been investigated before, as well as other methods such as Voting. Different weighting schemes for Weighted Voting were tested, and we present Algorithm 1 and 2, which are the theoretically and experimentally optimal weighting schemes respectively. Our work serves as a guideline for choosing ensemble methods for MDNNs.

In this work, we solve nonlinear systems of ordinary differential equations coupled to noisy forcing, commonly used for models of neurons such as the Hodgkin-Huxley equation, over a memristor crossbar based computing system. We demonstrate stability and faithfulness of the distributions even under the effects of nonidealities of the memristors and the system itself. We investigate the properties of the dynamical systems under quantization faithfulness, varying the level of precision of the fixed point integer representation and concluding that 24 bits is enough for solution of the Hodgkin-Huxley equations, demonstrating that our solver can operate with both high precision and achieve speedups with low precision approximate computation.

Von Neumann architecture-based deep neural network architectures are fundamentally bottlenecked by the need to transfer data from memory to compute units. Memristor crossbar-based accelerators overcome this by leveraging Kir-choff's law to perform matrix-vector multiplication (MVM) in-memory. They still, however, are relatively inefficient in their device programming schemes, requiring individual devices to be written sequentially or row-by-row. Parallel writing schemes have recently emerged, which program entire crossbars simultaneously through the outer product of bit-line and word-line voltages and pulse widths respectively. We propose a scheme that leverages singular value decomposition and low-rank approximation to generate all word-line and bit-line vectors needed to program a convolutional neural network (CNN) onto a memristive crossbar-based accelerator. Our scheme reduces programming latency by 90% from row-by-row programming schemes, while maintaining high test accuracy on state of the art image classification models.

Responsive deep brain stimulation (DBS) requires recruiting deep brain structures without affecting the superficial neuronal population. Neurosurgeons widely use implanted electrodes, which are highly localized but invasive, to stimulate the deep brain. Temporally interfering stimulation (TIS) excites the deep brain non-invasively. This neuromodulation technique utilizes two high-frequency sinusoidal electric fields that do not recruit superficial neural structures but have a small frequency differential. The small differential causes a low-frequency interference envelope that stimulates deep regions and is steerable by changing the intensity of the electric fields without physically moving the electrodes. Using TIS as a non-invasive DBS method generates high-frequency stimulation artifacts at recording sites, which may saturate a conventional recording front-end. This paper presents a low-power bidirectional 64-channel CMOS neural-ADC that is immune to artifacts such as those in the TIS techniques or conventional biphasic stimulation. The presented DC-coupled chopped analog front-end leverages delta-spectrum shaping to remove electrode DC offset voltage and maintain the input impedance higher than 250 MΩ, which is sufficient for interfacing with non-invasive scalp electrodes. The AFE operates on the input signal difference to detect large and rapid stimulation artifacts. It incorporates both exponential tracking and boosted-rate sampling to recover within 100 μs. Upon recovery, the neural-ADC range and speed are reduced to achieve noise and power efficiency factors of 2.98 and 10.6, respectively. In vivo recordings from anesthetized mice demonstrate the unique capabilities of the presented architecture in resolving local field potentials from the surface and epidural electrodes.

In this work, we present a modification to the digital Wallace-based Gaussian Random Number Generator (GRNG) by implementing an in-memory memristive dot-product engine in place of the vector-matrix multiplication (VMM) stage. The dot-product engine provides an analog interface to the GRNG with statistical robustness and better resource efficiency. One modification with three different structures is proposed and evaluated by the statistical test pass rates and benchmarked against the digital implementations. The best-proposed modification achieved a 95.8% test pass rate for 100 iterative small pool generation while requiring 23.6% and 44.4% less power and area consumption.