An 8-bit asynchronous single-ended Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for the realization of a perovskite photovoltaic (PV) sensing application is presented. Various techniques have been proposed to enhance speed and power efficiency. A bootstrap transmission gate-based sample and hold circuit is proposed to improve sampling linearity and reduce power consumption. The sample and hold circuit is configured to operate at a 90% duty cycle, hence, giving it enough time for the conversion. A two-stage latch dynamic comparator is implemented to ensure high-speed and low power consumption. The SAR ADC also implements an asynchronous SAR logic block, controlled by an internal clock, which eliminates the need for an external clock. The proposed SAR ADC was designed in a UMC 180nm CMOS technology. The SAR ADC is tested with a sinusoidal analog input of 500 mV at 10 kHz frequency and a 4 MHz input clock frequency. The SAR ADC consumes a power of 2.67 mW at a supply of 1.5 V. The proposed ADC is an important unit for application in the fast growing perovskite-based PV industry.

This paper presents the enhancement of Legendre Optimum low pass filters in terms of reusability and bandwidth, based on the variable or programmable memristance of memristors. Two low pass filters, of third and fifth order, operating in the radio frequency range, and designed using the insertion loss method are presented. At 600 KHz and at 110 MHz, two MS memristor models, of the non-linear ion drift class is incorporated into the filter circuits in turn and their memristances varied such that R_off- R_on decreases monotonically and R_off- R_on>0. Results show a bandwidth enhancement of up to 100 KHz at 600 KHz, and up to 19MHz at 110MHz. This study also examines the effect of the simultaneous versus asynchronous variation of the memristance of the pair of memristors introduced into the filter circuits, as well as increase in filter order.