Lab 9 introduced the use of memory in order to use the data in a text file to run an audio player. I was able to compile the provided circuit and send an audio file over the serial port to the FPGA which played the song. This lab was very useful in demonstrating the use of on board memory in the context of file i/o which is an extremely useful part of any digital circuit that does not do a specific task or needs to access data that is store on an external device like a hard drive.

ABSTRACT

Lab 8 explored the use of an RS232 port to communicate between the FPGA and pieces of circuits that are off of the board. I was able to compile a circuit which listened to the port and transmitted the incoming signal back over the RS232 port to display it on the serial port of a computer. This lab was very useful in showing how one would connect an FPGA to more complicated circuitry and transmit data between the two, allowing the FPGA to add as a central microprocessor for a more complicated lab.

Lab 7 instructed me to build an 8-bit triangle-wave and sine-wave generator. After building the triangle-wave generator I designed a sine-wave generator by using the output of the triangle wave as the read address for a ROM block which had the appropriate values in order to generate a since wave over the correct period. This lab was extremely useful in demonstrating how one can use a ROM block in order to save data that needs to be reproduced at a later time, an extremely common task in designing complicated circuits.

The core rotation rates of massive stars have a substantial impact on the nature of core collapse supernovae and their compact remnants. We demonstrate that internal gravity waves (IGW), excited via envelope convection during a red supergiant phase or during vigorous late time burning phases, can have a significant impact on the rotation rate of the pre-SN core. In typical (10 M⊙ ≲ M ≲ 20 M⊙) supernova progenitors, IGW may substantially spin down the core, leading to iron core rotation periods $P_{\rm min,Fe} \gtrsim 50 \, {\rm s}$. Angular momentum (AM) conservation during the supernova would entail minimum NS rotation periods of $P_{\rm min,NS} \gtrsim 3 \, {\rm ms}$. In most cases, the combined effects of magnetic torques and IGW AM transport likely lead to substantially longer rotation periods. However, the stochastic influx of AM delivered by IGW during shell burning phases inevitably spin up a slowly rotating stellar core, leading to a maximum possible core rotation period. We estimate maximum iron core rotation periods of $P_{\rm max,Fe} \lesssim 10^4 \, {\rm s}$ in typical core collapse supernova progenitors, and a corresponding spin period of $P_{\rm max, NS} \lesssim 400 \, {\rm ms}$ for newborn neutron stars. This is comparable to the typical birth spin periods of most radio pulsars. Stochastic spin-up via IGW during shell O/Si burning may thus determine the initial rotation rate of most neutron stars. For a given progenitor, this theory predicts a Maxwellian distribution in pre-collapse core rotation frequency that is uncorrelated with the spin of the overlying envelope.

Lab 6 instructed us to design a digital to analog converter in order to generate a square wave which would drive a speaker connected to the supplied FPGA. We also needed to be able to set the amplitude of the generated signal using the DIP switches present. This lab was very useful to show the basic theory behind digital to analog converters which need to turn digital values into actual signals. Also, this square wave generator is very useful in creating complicated audio signals which are composed of square waves of varying frequency.

Lab 5 instructed us to design a stopwatch using the supplied FPGAs. The circuit needed to be able to increment every tenth of a second and track the number of minutes and hours that had passed. While I was instructed to make a three-state machine that is driven by one button that causes the timer to stop/stop/reset in that order. However, I implemented a two-state system and attached the reset functionality to a second button in order to reflect the design of stopwatches that I had encountered. This lab was very useful in demonstrating the steps that are involved when creating a complete circuit. This included designing state machines as well as importing modules previously defined as external libraries which are extremely common when designing circuits.

Why do quick brown foxes jump over lazy dogs anyway? From a sociological perspective, it's useful to think about our judgmental attitude to laziness and speed and the way we theorise about sport.

Hello, welcome to the online curriculum for the Authorea hands-on session at ResBaz! This curriculum is intended to walk you through the exercises and challenges that we will cover during the Authorea workshop. You can access it at HTTP://AUTHOREA.COM/18566/.

WORDS ARE IMPORTANT. THEY CONVEY OUR THOUGHTS, OUR IDEAS, OUR INTUITIONS. PASSION, LOVE, DISCOVERY, THEY ALL MATERIALIZE FROM WORDS EMERGING FROM THE INNER WORKINGS OF OUR MINDS. AND WHEN WE WRITE, WHEN WE FILL WITH WORDS THE EMPTY CANVAS IN FRONT OF US, SOMETIMES THOSE INTUITIONS, THOSE FEELINGS, THOSE BEAUTIFUL BUNDLES OF THOUGHTS, THEY SUDDENLY BECOME CLEARER. ALL OF THE SUDDEN WE REALLY UNDERSTAND. THE WRITERS. THE READERS. THE LOVERS. TO LOVE, PASSION, DISCOVERY. TO WORDS. Happy Writing, - Matteo and The Authorea Team

Lab 4 emphasized common situations that one would encounter when building complex digital circuits. The first part looked at positive edge triggers which are a very useful way of getting a short pulse to start the logic for a particular circuit without having to worry about the length of time with which the original signal is high. The second part applied this positive edge trigger in the context of a debouncing element which is an extremely useful cirtcuit when using a switch or some other imperfect interface to start your circuit. And finally, the third section illustrated the ability of quartus to design submodules that can be replicated without the need to think about the underlying logic. This capability is extremely powerful and increases the overall readability and reusability of the designs.

The web application at feynman.aivazis.com is an attempt to provide the quality of diagrams that is producible in similar packages with the ease of use and portability that is found only on the web. By allowing the user to create diagrams at any Internet-connected device, feynman aims to be a complete solution for producing and exporting production-ready diagrams with as little effort by the user as possible. The only prerequisite in order to fully benefit from the application is to download the LaTeX drawing package that is used by the system if the diagram is to be exported to LaTeX. [1] [1] This package is available for download at feynman.aivazis.com/package as well as when the diagram is successfully exported to LaTeX.

G’DAY- AUTHOREA’S AUSTRALIA TOUR (AU♥AU) STARTS NEXT WEEK! Our co-founders, Nate and Alberto, will be down in Oz for the Research Bazaar conference at the University of Melbourne. We’re so very excited to hang out with our friends at UniMelb and make some new friends in the Melbourne area (and beyond!). We’re working on completing our schedule of speaking engagements. Below is a rough schedule of events/talks/demos that will take place during the tour. We will be updating it as we go along.

INTRODUCTION Part 1 of this lab involved the implementation of a simple counter using a Quartus Megafunction. After hooking up the counter to the FPGA’s onboard clock, I tested that the counter worked as intended. Then, using Quartus’s simulation features, I was able to look at the individual logic states of the parts of my logic both by tying the line to an output line on the board as well as using registers which were able to provide byte level inspection at any location on the board. Using an iPhone, I was able to record the clock as it incremented. In the 10 seconds I recorded the counter, it incremented 1.99 × 10⁹ times which gives the clock a period of ${1.9\times10^9} = 50.25 MHz$ Which is pretty close to the 50 MHz that is expected by the FPGA. After timing the clock, I simulated its performance using the Quartus simulator and verified that the counter incrememented to the right value at the right time. The 2nd part of the lab involved the creation of a binary-coded decimal counter which was made out of 5 up counters with a modulus of 10 as described in Section 2.2. In order to drive the system every hundredth of a second, I connected the FPGA’s CLOCK_50 to a modulus 500000 counter whose cout went high at the desired frequency. Part 3 of the lab involved the creation of a 4 bit counter from elementary gates and a D flop. I did use a Quartus megafunction in order to create a modulus counter that would drive the system every second. In constructing this diagram, I needed to create a 1 bit adder without a carry-in (done with an xor and and) 1 bit multiplexer (created with an inverter) which acts as the carry-in for the counter as a whole.

We’re very happy to announce a special TRAVEL GRANT for European FGSA and FIP members attending the AMERICAN PHYSICAL SOCIETY APS MARCH MEETING 2015, in San Antonio, Texas. Authorea is committed to helping the advancement of scientific collaboration and this travel grant aims to foster the interexchange between young EU and US members, helping students and postdoc to integrate in the international APS community and to share their different experiences. These travel grant will be recognized at the Student and FIP Receptions, during the March Meeting 2015. For more information on the travel grant and application instructions please visit http://www.aps.org/units/fgsa/travel/ and http://www.aps.org/units/fip/awards/travel-grant.cfm.

Interactive figures in Authorea documentsAuthorea enables embedding of interactive, dynamic, data-driven figures directly into articles. These can be diagrams from external services like CartoDB or diagrams from a javascript library like d3.js, flotchart, or bokeh.To insert an interactive figure, click Insert Interactive Figure  from the toolbar and select the HTML file that you wish to add to your document. 

GOODBYE SOHO, HELLO GRAMERCY! Today we move Authorea’s HQ to a new office in the Gramercy Park area of New York City. We’re excited to move to a bigger, brand new office (with windows!) in this “exclusive neighborhood boasting cute shops, cool taverns, and one very special members-only park” (yep, this is how Airbnb depicts Gramercy Park). Update your address book and come say hi. Authorea’s new address is: Authorea 120 E 23rd Street 5th Floor New York, New York 10017

We’re launching #Institutions today! Since the beginning of Authorea, it’s been our mission to work closely with universities, departments, research labs, and libraries to help them manage and curate scholarly content. So, what’s new? You can now: 1. Browse institutions and find yours! If it’s missing, let us know and we’ll add it. 2. Add your affiliation(s) to your profile. Just log in and click on User Settings in your profile. 3. Let your librarian or PI know about #institutions at Authorea, so that they can claim and manage their institutional page.